Control and status for direct serial mode
Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported.
| EN | Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled. |
| BUSY | Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can’t halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) |
| ASSERT_CS0N | When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0. |
| ASSERT_CS1N | When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0. |
| AUTO_CS0N | When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. |
| AUTO_CS1N | When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. |
| TXFULL | When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. |
| TXEMPTY | When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. |
| TXLEVEL | Current level of DIRECT_TX FIFO |
| RXEMPTY | When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. |
| RXFULL | When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. |
| RXLEVEL | Current level of DIRECT_RX FIFO |
| CLKDIV | Clock divisor for direct serial mode. Divisors of 1…255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. |
| RXDELAY | Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) |